Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic

摘要

A new asynchronous early output section-carry based carry lookahead adder(SCBCLA) with alias carry output logic is presented in this paper. To evaluatethe proposed SCBCLA with alias carry logic and to make a comparison with otherCLAs, a 32-bit addition operation is considered. Compared to theweak-indication SCBCLA with alias logic, the proposed early output SCBCLA withalias logic reports a 13% reduction in area without any increases in latencyand power dissipation. On the other hand, in comparison with the early outputrecursive CLA (RCLA), the proposed early output SCBCLA with alias logic reportsa 16% reduction in latency while occupying almost the same area and dissipatingalmost the same average power. All the asynchronous CLAs arequasi-delay-insensitive designs which incorporate the delay-insensitivedual-rail data encoding and adhere to the 4-phase return-to-zero handshaking.The adders were realized and the simulations were performed based on a 32/28nmCMOS process.